1. Field of the Invention
The present invention relates to flash memory device testing, and more particularly, the present invention relates to a flash memory device having a fuse cell array and a method of testing a flash memory device.
2. Description of the Related Art
Recently, various flash memory devices have been developed, which include additional circuits, such as a controller and a voltage regulator, as well as a flash fuse cell array. Most flash memory devices normally operate at voltage of about 1V through 3V. However, a high voltage, which may be several times the normal voltage, is required for erase, program and read operations. Therefore, the regulator of a flash memory device is a kind of a DC to DC converter, which generates a high voltage from a low voltage and provides the high voltage to a flash memory cell array having multiple memory cells.
However, because of errors which may occur during the semiconductor fabrication process, the regulator may not generate the required high voltage. Because the level of the high voltage affects stability and life span of products, and because errors in a semiconductor fabrication process are inevitable, a general test process measures the voltage output from the regulator and appropriately corrects the voltage using a trim circuit. The trim circuit includes a fuse circuit that is set to output a trim code for correcting the errors in the voltage. The regulator receives the trim code from the fuse circuit and outputs the corrected high voltage.
A conventional fuse circuit includes a fuse array that connects or disconnects internal fuses, as needed, using a laser, etc. A limitation of the fuse array is that a trim code is set only one time.
FIG. 1 is a block diagram illustrating a conventional flash fuse cell array.
Referring to FIG. 1, a flash fuse cell array 10, acting like a fuse, turns programmable flash cells 11 through 18 on/off and generates trim codes TR0 through TR3 through sense amplifiers 19A through 19D, respectively. The trim codes TR0 through TR3 are applied to a voltage control unit of a regulator (not shown) and are used by the regulator to output the appropriate voltage. Even when the power is off, each of the flash cells 11 through 18 may maintain the set trim codes and may reset the trim codes since the flash cells are non-volatile.
The flash fuse cell array 10 may store two kinds of trim codes. When a first word line W0 and each of bit lines B0 through B3 are activated, a first trim code is output. When a second word line W1 and each of the bit lines B0 through B3 are activated, a second trim code is output. Source lines S0 and S1 are generally connected to a ground voltage.
FIG. 2 is a block diagram illustrating a conventional flash memory device.
Referring to FIG. 2, in a high voltage output test of a flash memory device, a high voltage regulator 20 outputs a predetermined high voltage VPP according to a default code output from a flash fuse cell array, such as the flash fuse cell array 10 of FIG. 1. The regulator 20 includes a decoder 21, a reference voltage generator 22, a voltage control unit 23, and a pumping unit 24. The decoder 21 decodes an input trim code. For example, when a 4-bit trim code (TR0 through TR3) is provided to the decoder 21, the decoder 21 decodes the trim code and provides 16-bit binary codes D0 through D15. The reference voltage generator 22 generates a reference voltage VR. The voltage control unit 23 includes a series resistor array RL, R0 though R15, and switches that may change the connection of resistors. When a total resistance of the resistor array is changed according to the binary codes, a voltage applied to the pumping unit 24 can be changed, and thus controlling a level of the high voltage VPP.
A tester 25 measures the high voltage VPP, and compares the level of the high voltage VPP with a level of a required high voltage, and generates a pertinent trim code signal TRIM CODE according to the result of the comparison. The trim code TRIM CODE is again applied to the flash fuse cell array 10, and is stored in the flash cells of the flash fuse cell array 10.
However, it is often necessary to temporarily change the level of the high voltage VPP of the regulator 20, according various types of tests which may be performed after correcting the regulator 20. In a conventional flash memory device, whenever the level of the high voltage VPP must changed, the trim code TRIM CODE for the high voltage VPP of the changed level must be stored in the flash fuse cell array 10. Generally, in the mass production of flash memory devices, the produced devices are simultaneously tested. However, memory devices with different correction characteristics cannot be simultaneously tested by the conventional method.